1. Field of the Invention
The present invention relates to wide or multiple input OR gates used to implement the "sum" of the "sum of product terms" in a programmable logic device (PLD). More particularly, the present invention relates to circuitry for a zero-power wide OR gate responsive to a sleep mode signal to reduce power consumption and having circuitry allowing a reduced recovery time from a sleep mode.
2. Description of the Prior Art
Prior Art PLD
Utilizing a Wide OR gate
FIG. 1 shows an array structure for a typical prior art programmable array logic (PAL) device, a type of PLD which utilizes a multiple input OR gate to implement the "sum" to produce a "sum of product terms" output.
The PAL of FIG. 1 has six inputs I.sub.0-5 and four outputs O.sub.0-3. The inputs I.sub.0-5 each have a true output 104 and a complement output 106 forming rows connected to programmable array cells, such as programmable array cell 110, of programmable array cells 108. An array cell, such as cell 110, may be programmed to be connected or disconnected to an AND gate in the AND array 100. Groups of array cells programmed to be connected to an AND gate in AND array 100 form a "product term" of the "sum of product terms" output. The AND array 100 is followed by an OR array 102. Each OR gate in the OR array 102 is connected to one or more AND gates in AND array 100 to provide the "sum" of the "sum of product terms" output.
Although the OR gates in OR array 102 are shown with fixed connections to a number of AND gates in AND array 100, some PAL circuit configurations allow each OR gate in OR array 102 to be programmably connected to any AND gate output in AND array 100. The OR gates in OR array 102 may also have outputs connected to an output logic macrocell 114 which is programmable to be either registered or combinatorial. Circuitry similar to that shown in FIG. 1, including the output logic macrocell 114, is utilized on the AmPALCE22V10, a device manufactured by Advanced Micro Devices, Inc.
To assure sufficient voltage is provided to OR gates in OR gate array 102 at a high speed, sense amplifiers are utilized by manufacturers to implement the AND gates in the AND array 110. Sense amplifiers convert a small voltage from the product term into a larger, rail to rail, voltage at a high speed to drive an OR gate. Circuitry for sense amplifiers utilized to implement an AND gate to create a "product term" portion of the "sum of product terms" output for a PAL device is shown in copending U.S. application Ser. No. 08/118432 entitled "Latching Zero-Power Sense Amplifier With Cascode" which is incorporated herein by reference.
Prior Art
Wide OR Gates
FIG. 2A shows circuitry for a prior art CMOS wide OR gate 200. The wide OR gate 200 includes several input NOR gates 202, with each NOR gate in NOR gates 202 receiving two signals from input signals SA1-SA16. The input signals SA1-SA16 are provided by sense amplifiers used to implement AND gates as discussed above with respect to FIG. 1. Outputs of NOR gates 202 are provided in pairs to inputs of NAND gates 204. The outputs of NAND gates 204 are provided as inputs to NOR gates 206. The outputs of NOR gates 206 are provided as inputs to NAND gate 208. The cascading of NOR gates 202, NAND gates 204, NOR gates 206, and NAND gate 208 forms a binary tree so that NAND gate 208 can provide the OR output of wide OR gate 200. An inverter 210 is further connected to the output of NAND gate 208 to also provide a NOR output for wide OR gate 200.
Circuitry for individual NOR gates of NOR gates 202 and 206 is shown in FIG. 2B. The NOR gate of FIG. 2B includes two p-channel transistors 220 and 222 and two n-channel transistors 224 and 226. The circles on transistors, such as transistors 220 and 222, indicate a p-channel transistor,- while no circle indicates an n-channel transistor. P-channel transistor 220 has a source connected to V.sub.DD and a drain connected to the source of p-channel transistor 222. The drain of p-channel transistor 222 is connected to the drain of n-channel transistors 224 and 226 and provides the NOR gate output. The sources of transistors 224 and 226 are connected to V.sub.SS. The two inputs of the NOR gate are coupled to one p-channel transistor of transistors 220 and 222 and one n-channel transistor of transistors 224 and 226 respectively.
Circuitry for individual NAND gates of NAND gates 204 and 208 is shown in FIG. 2C. The NAND gate of FIG. 2C includes two p-channel transistors 230 and 232 and two n-channel transistors 234 and 236. The sources of p-channel transistors 230 and 232 are coupled to V.sub.DD, while their drains are coupled together and to the drain of n-channel transistor 234 to form the NAND gate output. The source of n-channel transistor 234 is coupled to the drain of n-channel transistor 236, and the source of transistor 236 is coupled to V.sub.SS. The two inputs of the NAND gate are coupled to one p-channel transistor of transistors 230 and 232 and one n-channel transistor of transistors 234 and 236 respectively.
The circuitry of FIG. 2A is ideal to implement relatively narrow NOR gates. The wide OR gate 200 of FIG. 2A, however, has drawbacks. First, the wide OR gate 200 is not well suited for more than eight inputs because of a comparatively high transistor count. Each two input gate consists of four transistors so that ultimately, because of cascading used in the binary tree, each input adds roughly four transistors. Second, wide OR gate 200 has a speed disadvantage as compared to other circuits.
FIG. 3A shows circuitry for a prior art CMOS OR gate 300 having a lower transistor count than the wide OR gate 200 of FIG. 2A. The wide OR gate 300 includes input NOR gates 302, each NOR gate of NOR gates 302 receiving four of input signals SA1-SA16. The outputs of NOR gates 302 are provided to a single NAND gate 304. The output of NAND gate 304 forms the OR output of wide OR gate 300. An inverter 306 is further connected to the output of NAND gate 304 to also provide a NOR output for wide OR gate 200.
Circuitry for individual NOR gates of NOR gates 302 is shown in FIG. 3B. The NOR gate of FIG. 3B includes four p-channel transistors 311-314 and four n-channel transistors 321-324. P-channel transistors 311-314 have current paths between their source and drain connected in series between V.sub.DD and the output of the NOR gate. N-channel transistors 321-324 have drains coupled to the output of the NOR gate, and sources coupled to V.sub.SS. Each of the four inputs of the NOR gate are coupled to one p-channel transistor of transistors 311-314 and one n-channel transistor of transistors 321-324 respectively.
Circuitry for four input NAND gate 304 is shown in FIG. 3C. The NAND gate of FIG. 3B includes four p-channel transistors 331-334 and four n-channel transistors 341-344. N-channel transistors 341-344 have current paths between their source and drain connected in series between the output of the NAND gate and V.sub.SS. P-channel transistors 331-334 have drains coupled to V.sub.DD and sources coupled to the output of the NAND gate. Each of the four inputs of the NAND gate are coupled to one p-channel transistor of transistors 331-334 and one n-channel transistor of transistors 341-344 respectively.
Although the wide OR gate 300 of FIG. 3A has a comparably lower transistor count than the wide OR gate 200 of FIG. 2A, the wider OR gate 300 of FIG. 3A has an even greater speed disadvantage than the OR gate 200 of FIG. 2A.
Prior Art
Zero-Power Devices
With the introduction of notebook computers and other devices utilizing battery power, electronic circuits in the devices are required to utilize as little power as possible to preserve the batteries for an extended period of time. Even with devices which are not battery powered, it is desirable to have electronic circuits which operate with as little power consumption as possible to conserve energy, thus reducing operational costs.
Manufacturers have developed specialized electronic parts, called zero power parts, for use in battery powered devices such as notebook computers. The zero power parts have a low power consumption mode, also referred to as a sleep mode, which is entered when the zero power part has not been accessed for a period of time. To create the sleep mode, a sleep mode signal is developed by circuitry in the zero-power part and is transmitted in a true state to turn off internal components of the zero power part when an input signal has not been received for a period of time. The sleep mode signal is transmitted in a complement state to power up, or wake up the internal components of the zero-power part from a sleep mode when another input signal to the zero-power part is received.
For the AmPALCE22V10 discussed above, a zero power version, the AmPALCE22V10Z-25, is also available from Advanced Micro Devices, Inc. The AmPALCE22V10Z-25 operates at a lower speed than non zero-power versions because it requires time to be powered up from a sleep mode.
Prior Art Wide OR Gate
Utilized on Zero-Power Device
Because of the design of zero-power sense amplifiers used to implement AND gates on the AmPALCE22V10Z-25, the wide OR gates utilized are specially designed to be compatible. Zero-power sense amplifiers on the AmPALCE22V10Z-25 have outputs placed in a low state during sleep mode to conserve power. When an input transition is detected causing the zero-power components to power up from sleep mode, the zero-power sense amplifiers require a recovery time period to return to a high state if necessary.
Because the zero-power sense amplifiers go to a low state during sleep mode, unlike the OR gates of FIGS. 2A and 3A, OR gates on the AmPALCE22V10Z-25 include circuitry to latch their output to the state of the previous wake mode during sleep mode to prevent the OR gate outputs from being affected. Also, because of the time delay for the sense amplifier to power up, OR gates on the AmPALCE22V10Z-25 include circuitry to delay power up until after the sense amplifiers have had time to recover to avoid outputting an erroneous signal.
The zero-power wide OR gate 400 utilized on the AmPALCE22v10Z-25 is shown in FIG. 4. To receive the sense amplifier inputs, wide OR gate 400 includes n-channel transistors 402.sub.1 -402.sub.n which receive input signals SA1-SAn from sense amplifiers at their gates. The sources of transistors 402.sub.1 -402.sub.n are coupled to V.sub.SS, while the drains are coupled to a current source transistor 404 at node 401.
To latch the previous state of the OR gate during a sleep mode, the OR gate 400 further includes a latch formed by inverters 406 and 408. A connection between inverters 406 and 408 is labeled 411. The latch 406,408 is connected at node 411 through the current path formed between the source and drain of a transistor 410 to node 401. A pair of transistors 412 and 414 have current paths connected in parallel between node 411 and inverter 408. Transistors 410 and 414 have gates coupled to a line PHI, while transistor 412 is coupled to a line PHIB. The line PHI carries a sleep mode signal indicating a sleep mode in a low state, while the line PHIB carries a sleep mode signal indicating the sleep mode in a high state.
To provide the OR output of wide OR gate 400, an inverter 416 is connected to node 411 and provides the OR output of wide OR gate 400 as its output. Further, an additional connection to node 411 provides a NOR output for wide OR gate 400.
In operation, we begin by assuming a first state where the sleep mode signal indicates an awake state with PHI being high and PHIB being low, and no sense amplifier output is high. With no sense amplifier high, none of transistors 402.sub.1 -402.sub.n will conduct and current source transistor 404 pulls node 401 high. With PHI high transistor 410 will further conduct making node 411 high.
With node 411 high, the NOR output will be high and the OR output through inverter 416 will be low. With PHI high and PHIB low, transistors 412 and 414 will be off isolating the output of inverter 408. Because node 411 is high, the output of inverter 406 will be low, while the output of inverter 408 will be high.
If any of sense amplifier outputs SA1-SAn go high, the associated transistor 401.sub.1 -401.sub.n will conduct, overcoming the current from transistor 404 thus pulling node 401 low. Because PHI is still high, transistor 410 will conduct pulling node 411 low and further pulling the NOR output high and the OR output low. With PHIB remaining low, transistors 412 and 414 will remain off isolating the output of inverter 408. Since node 411 is low, the output of inverter 406 will go high while the output of inverter 408 will go low.
We next assume a state where the sleep mode signal indicates a sleep state with PHI being low and PHIB being high, and no sense amplifier output is high. With PHI low and PHIB high, transistors 412 and 414 are on and transistor 410 is off connecting the output of inverter 408 to node 411 and isolating node 401 which allows inverters 406 and 408 to latch the NOR output to the last state it was in prior to the sleep mode. The OR output will likewise retain its state prior to the sleep mode.
Because all of the sense amplifier outputs SA1-SAn will go low during sleep mode to conserve power in the sense amplifier, transistors 402.sub.1 -402.sub.n will all turn off allowing transistor 404 to pull node 401 high. Node 401 will, therefore, always be high in the sleep mode regardless of its state during the prior wake mode. Because of a time delay required for the sense amplifier which is in a high state prior to the sleep mode to power up and return from a low state to the high state during the next wake mode, wide OR gate 400 might produce an erroneous output for a short period. To prevent OR gate 400 from producing an erroneous output, circuitry (not shown) is provided to delay PHI and PHIB to the NOR gate until after the sense amplifiers have recovered from sleep mode.
As discussed above, to be compatible with a sense amplifier of the AmPALCE22V10Z-25 which does not latch its previous state, the wide OR gate 400 latches its output during sleep mode and includes circuitry (not shown) to delay power up until the sense amplifiers have had time to recover from sleep mode. Additionally, since the wide OR gate 400 latches a portion of its data path, additional time delay is provided to enable the OR gate 400 to recover from a sleep mode. Coincidentally, however, the design of the wide OR gate 400 typically offers a speed advantage and requires less space on a silicon chip than both OR gates of FIGS. 2A and 3A since only one additional transistor is required for each additional sense amplifier input.
Unlike sense amplifiers utilized on the AmPALCE22V10Z-25, however, more recent sense amplifiers are designed to latch their previous state in sleep mode while still consuming negligible power. Such a zero-power sense amplifier is disclosed in the copending U.S. application Ser. No. 08/118,432 entitled "Latching Zero-Power Sense Amplifier With Cascode", incorporated herein previously.